High data reliability, high speed of memory access, reduced chip size and reduced power consumption are features that are demanded from semiconductor memory.
In conventional peripheral circuitries for a semiconductor device, for example, pads and data queue circuits (or data input/output circuits) are arranged in a corresponding manner across layers. The data queue circuit or data input/output circuit is called collectively “DQ circuit” hereinafter. A sub-threshold current reduction circuit (SCRC) has been introduced into conventional semiconductor devices to protect a circuit from an off-state current (Ioff) into a critical path when the chip (die) is in an off state. FIGS. 1A and 1B are circuit diagrams of a sub-threshold current reduction circuit (SCRC) in a conventional semiconductor device. In the SCRC, a high power supply voltage VOL(Hi) and a low power supply voltage VOL(Lo) indicate power supply voltages applied to a semiconductor device from an external, and a high SCRC voltage VOLSCRC(Hi) and a low SCRC voltage VOLSCRC(Lo) indicate internal SCRC power voltages applied through switches of the SCRC (VOLSCRC SW) to logic circuits such as inverters.
FIG. 2A is a layout diagram of a plurality of switches of the SCRCs (VOLSCRC SWs) in a conventional semiconductor device. FIG. 2B is a circuit diagram of the plurality of switches of the SCRCs (VOLSCRC SWs) in the conventional semiconductor device of FIG. 2A. The switches of the SCRCs (VOLSCRC SWs) are located near logic circuits, regardless of operation types of the logic circuits, and configured to couple VOL lines having the power supply voltage VOL to VOLSRCS lines having the SCRC voltage VOLSCRC in order to generate the SCRC voltage VOLSCRC. In a conventional semiconductor chip, the power supply voltage VOL may be provided from an uppermost-level conductive layer including a pad (e.g., an inline redistribution layer (iRDL)) to an M3 pad on a metal 3 level layer that may provide the power supply voltage VOL on the VOL lines throughout the chip, and the switches of the SCRCs (VOLSCRC SWs) are located near the logic circuits to provide the SCRC voltage VOLSCRC. Each switch of the SCRC (VOLSCRC SW) has a size approximately three times to five times of a size of each transistor in logic circuits driven by the VOLSCRC SW to prevent a voltage (IR) drop that occurs locally due to the logic circuits that operate irregularly Each switch of the SCRC (VOLSCRC SW) also propagates an IR drop on the VOL lines to the VOLSCRC lines that causes a local area dependency in the chip resulting in time lags and the VOLSCRC SW area needs to be designed large enough to prevent such IR drop propagation.